Logic Design Model Question Paper:

B.E Third Semester Examination, Dec-2010

Model Paper

On

LOGIC DESIGN

1                    (a) Reduce the function using K-map technique

F(A, B, C, D, E) = Σ m (1, 4, 8, 10, 11, 20, 22, 24, 25, 26) + d(0, 12, 16, 17)

                                                                                                (8 Marks)

      (b) The input to a combinational logic circuit is a 4-bit binary number. Design the logic circuit with minimum hardware for the following.

i) Output y₁=1 if the input binary number is 5 or less than 5.

ii) Output y₂=1 if the input binary number is 9 or more than 9.         (8 Marks)

(c) Show that A Θ B Θ C Θ D = Σm(0, 3, 5, 9, 10, 12, 15)               (4 Marks)

2                    (a) Solve by Quine-McCluskey method.

F(A, B, C, D, E, F) = Σ (6, 9, 13, 18, 19, 25, 27, 29, 41, 45, 57, 61)

                                                                                          (10 Marks)

(b) Using Quine-McCluskey tabulation method, obtain the set of prime implicants for the function

 f (a, b, c, d)= Σ (0, 1, 4, 5, 9, 10, 12, 14, 15) + Σ ϕ(2, 8, 13)

and hence obtain the minimal form of the given function emplying decimal representation.                                                            (10 Marks)

    

     3     (a) Explain BCD to seven segment display decoder with K-map and also draw the logic diagram for the same.                                                               (12 Marks)

            (b) What is an encoder? Explain on8-to-3 line encoder.         (8 Marks)

4        (a) Implement f ( a, b, c, d) = Σ m(0, 1, 5, 7, 9, 10, 15) using

a.       8:1 MUX with b, c, d as select lines

b.      4:1 MUX with a, d as select line.

(12 Marks)

                  (b) What is Comparator? Briefly explain the organization of a 1-bit comparator.                                                                                               (8 Marks)

     5     (a)  Differentiate following

            i) Combinational circuit and Sequential circuit.

            ii) Synchronous sequential circuit and Asynchronous sequential circuit.

                                                                                                            (10 Marks)

            (b) Explain following

            i) Master Slave JK flip flop.

            ii) Switch debouncer using SR latch.                                      (10 Marks)

6        (a) Explain with suitable logic and timing diagram.

i) Serial-in-Serial-out         ii) Parallel-in-Parallel-out        (12 Marks)

(b) With diagram explain universal shift register. (8 Marks)

     7     (a) With a suitable example, explain Melay and Moore model in a sequential circuit analysis.                                                                                 (10 Marks)

            (b) Design a Synchronous Mod-6 counter using clocked SR flip-flop. And also explain the Ripple counter.                                                                        (10 Marks)

8        (a) Design a synchronous counter for

 4-->6-->7-->3-->1------ 4…

Avoid lockout condition. Use JK type design.                            (12 Marks)

      (b) With a suitable example and appropriate state diagram, explain how to recognize a particular sequence. Ex: 1100. (Any sequence can be assumed).

                                                                                                      (8 Marks)

                                          ******************