HDL Programming for 1 to 4 Demultiplexer

VHDL File Name:

demux1to4.vhd
-- Demux1to4 - Behavioral
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity demux1to4 is
Port ( en    : in  STD_LOGIC;
sel   : in  STD_LOGIC_VECTOR(1 downto 0);
a_in  : in  STD_LOGIC;
y_out : out  STD_LOGIC_VECTOR (3 downto 0));
end demux1to4;
architecture Behavioral of demux1to4 is
begin
process(en,sel,a_in)
begin
if(en /= '0') then  -- Active Low Enabled
y_out <= "ZZZZ";
else
y_out <= "0000";
case sel is
when "00" => y_out(0) <= a_in;
when "01" => y_out(1) <= a_in;
when "10" => y_out(2) <= a_in;
when "11" => y_out(3) <= a_in;
when others => y_out <= "ZZZZ";
end case;
end if;
end process;
end Behavioral;

Verilog File Name:

demux1to4.v
// Demultiplexer 1 to 4
module demux1to4(en,sel,a_in,y_out);
input      en;
input [1:0]  sel;
input      a_in;
output [3:0] y_out;
wire    en;
wire [1:0] sel;
wire    a_in;
reg  [3:0] y_out;
always@(en,sel,a_in)
begin
if(en != 0) // Active Low Enabled
y_out = 4'bZZZZ;
else
begin
y_out = 4'b0000;
case(sel)
2'b00   :  y_out[0]  = a_in;
2'b01   :  y_out[1]  = a_in;
2'b10   :  y_out[2]  = a_in;
2'b11   :  y_out[3]  = a_in;
default   :  y_out = 4'bZZZZ;
endcase
end
end
endmodule