HDL Programming for 4Bit Binary to Gray Converter

VHDL File Name:

bin_to_gray_4bit.vhd
-- Binary to Gray 4 bit converter - Dataflow
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity bin_to_gray_4bit is
Port ( b_in : in  STD_LOGIC_VECTOR (3 downto 0);
g_op : out  STD_LOGIC_VECTOR (3 downto 0));
end bin_to_gray_4bit;
architecture Dataflow of bin_to_gray_4bit is
begin
g_op(3) <= b_in(3);
g_op(2) <= b_in(3) xor b_in(2);
g_op(1) <= b_in(2) xor b_in(1);
g_op(0) <= b_in(1) xor b_in(0);
end Dataflow;

Verilog File Name:

bin_to_gray_4bit.v
// Binary to Gray 4bit Converter
module bin_to_gray_4bit( b_in, g_op );
input  [3:0] b_in;
output [3:0] g_op;
wire [3:0] b_in;
reg  [3:0] g_op;
always @ (b_in)
begin
g_op[3] = b_in[3];
g_op[3] = b_in[3] ^ b_in[2];
g_op[3] = b_in[2] ^ b_in[1];
g_op[3] = b_in[1] ^ b_in[0];
end
endmodule