HDL programming for 2 to 4 Decoder

Programming for 2 to 4 decoder:

VHDL File Name:

decoder2to4.vhd
-- decoder2to4 - Behavioral
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoder2to4 is
Port ( d_in   : in  STD_LOGIC_VECTOR (1 downto 0);
en    : in  STD_LOGIC;
d_op  : out  STD_LOGIC_VECTOR (3 downto 0));
end decoder2to4;
architecture Behavioral of decoder2to4 is
begin
process(en,d_in)
begin
if(en/='0')then -- Active Low Enabled
d_op<="ZZZZ";
else
case d_in is
when "00" => d_op <= "0001";
when "01" => d_op <= "0010";
when "10" => d_op <= "0100";
when "11" => d_op <= "1000";
when others => d_op <= "ZZZZ";
end case;
end if;
end process;

end Behavioral;

Verilog File Name:

decoder2to4.v
// decoder2to4
module decoder2to4( d_in, en, d_op );
input [1:0] d_in;
input en;
output [3:0] d_op;
wire en;
wire [1:0] d_in;
reg [3:0] d_op;
always @ (en, d_in)
begin
if(en) // Active Low Enabled
d_op = 4'bZZZZ;
else
begin
case (d_in)
2'b00 : d_op = 4'b0001;
2'b01 : d_op = 4'b0010;
2'b10 : d_op = 4'b0100;
2'b11 : d_op = 4'b1000;
default : d_op = 4'bZZZZ;
endcase
end
end
endmodule