HDL Programming for 4th sem Electronics

Program for all logic Gates:


VHDL File Name:

AlllogicGates.vhd
-- All Logic Gates -  DataFlow

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity AllLogicGates is
Port (a_in   : in  STD_LOGIC;
b_in   : in  STD_LOGIC;
not_op : out  STD_LOGIC;
and_op : out  STD_LOGIC;
nand_op : out  STD_LOGIC;
or_op  : out  STD_LOGIC;
nor_op : out  STD_LOGIC;
xor_op : out  STD_LOGIC;
xnor_op : out  STD_LOGIC);
end AllLogicGates;
architecture DataFlow of AllLogicGates is
begin
not_op  <=  not a_in;
and_op  <=  a_in and b_in;
nand_op  <=  a_in nand b_in;
or_op  <=  a_in or b_in;
nor_op  <=  a_in nor b_in;
xor_op  <=  a_in xor b_in;
xnor_op  <=  a_in xnor b_in;
end DataFlow;

Verilog File Name:

AlllogicGates.v
// All Logic Gates
module AllLogicGates( a_in, b_in, not_op, and_op, nand_op, or_op,
nor_op, xor_op, xnor_op );
input a_in, b_in;
output not_op, and_op, nand_op, or_op, nor_op, xor_op, xnor_op;
wire a_in, b_in;
reg not_op, and_op, nand_op, or_op, nor_op, xor_op, xnor_op;
always @ (a_in, b_in)
begin
not_op  = ~(a_in);
and_op  = a_in & b_in;
nand_op  = ~(a_in & b_in);
or_op  = a_in | b_in;
nor_op  = ~(a_in | b_in);
xor_op  = a_in ^ b_in;
xnor_op  = ~(a_in ^ b_in);
end
endmodule