HDL Programming for ALU 32 Bit

VHDL File Name:

alu32bit.vhd
--ALU32bit - Behavioral
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity alu32bit is
Port ( en   : in   BIT;
opc  : in  STD_LOGIC_VECTOR (3 downto 0);
a_in, b_in : in  STD_LOGIC_VECTOR (31 downto 0);
y_op : out STD_LOGIC_VECTOR (31 downto 0));
end alu32bit;
architecture Behavioral of alu32bit is
begin
process(en, a_in, b_in, opc)
begin
if (en = '1') then    -- Active High Enabled
case opc is
when "0001" => y_op<= a_in + b_in;
when "0010" => y_op<= a_in - b_in;
when "0011" => y_op<= not a_in;
when "0100" => y_op<= a_in and b_in;
when "0101" => y_op<= a_in or b_in;
when "0110" => y_op<= a_in nand b_in;
when "0111" => y_op<= a_in xor b_in;
when others=>null;
end case;
else
y_op <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
end if;
end process;
end behavioral;

Verilog File Name:

alu32bit.v
// ALU 32bit
module alu32bit( en, opc, a_in, b_in, y_op );
input en;
input [3:0] opc;
input [31:0] a_in, b_in;
output [31:0] y_op;
wire en;
wire [3:0] opc;
wire [31:0] a_in, b_in;
reg  [31:0] y_op;
always @ ( en, opc, a_in, b_in)
if (en == 1)  // Active High Enabled
case (opc)
4'b0001 : y_op = a_in + b_in;
4'b0010 : y_op = a_in - b_in;
4'b0011 : y_op = ~ a_in;
4'b0100 : y_op = a_in & b_in;
4'b0101 : y_op = a_in | b_in;
4'b0110 : y_op = ~ (a_in & b_in);
4'b0111 : y_op = a_in ^ b_in;
default null;
endcase
else
y_op  = 32'bZ;
endmodule