HDL Programming for Full Adder (Structural) including all

Full Adder Structural Description:

VHDL File Name:

full_adder_struct.vhd
-- Full Adder - Structural
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity full_adder is
port ( a_in, b_in, c_in : in  STD_LOGIC;
sum,carry : out  STD_LOGIC);
end full_adder;
architecture structural of full_adder is
component xor2_1
port(a, b : in STD_LOGIC;
y : out STD_LOGIC);
end component;
component and2_1
port(a, b : in STD_LOGIC;
y : out STD_LOGIC);
end component;
component or2_1
port(a, b : in STD_LOGIC;
y : out STD_LOGIC);
end component;
signal s1,s2,s3: STD_LOGIC;
begin
x1: xor2_1  port map (a_in, b_in, s1);
a1: and2_1  port map (a_in, b_in, s2);
x2: xor2_1  port map (s1, c_in, sum);
a2: and2_1  port map (s1, c_in, s3);
o1: or2_1 port map (s2, s3, carry);
end structural;

VHDL File Name:

xor2_1.vhd
-- xor2_1 - DataFlow
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity xor2_1 is
Port ( a,b : in  STD_LOGIC;
y : out  STD_LOGIC);
end xor2_1;
architecture data_flow of xor2_1 is
begin
y <= a xor b;
end data_flow;

VHDL File Name:

and2_1.vhd
-- and2_1 - DataFlow
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity and2_1 is
port ( a, b : in  STD_LOGIC;
y : out  STD_LOGIC);
end and2_1;
architecture data_flow of and2_1 is
begin
y <= a and b;
end data_flow;

VHDL File Name:

or2_1.vhd
-- or2_1 - DataFlow
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity or2_1 is
Port ( a,b : in  STD_LOGIC;
y : out  STD_LOGIC);
end or2_1;
architecture data_flow of or2_1 is
begin
y <= a or b;
end data_flow;

Verilog File Name:

full_adder_struct.v
//Full Adder - Structural
module full_adder( a_in, b_in, c_in, sum, carry );
input a_in, b_in, c_in;
output sum, carry;
wire s1,s2,s3;
//syntax: gate_operator lable (ouput, input, input);
xor x1 (s1, a_in, b_in);
and a1 (s2, a_in, b_in);
xor x2 (sum, s1, c_in);
and a2 (s3, s1, c_in);
or  o1 (carry, s2, s3);
endmodule