HDL Programming for Full Adder (Behavioral)

Full Adder Behavioral Description

VHDL File Name:

FullAdder_Behav.vhd
-- Full Adder - Behavioral
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FullAdder_Behav is
Port ( a_in, b_in, c_in : in  STD_LOGIC;
sum, carry : out  STD_LOGIC);
end FullAdder_Behav;
architecture Behavioral of FullAdder_Behav is
begin
process ( a_in, b_in, c_in)
begin
if(a_in='0' and b_in='0' and c_in = '0') then
sum <= '0';carry <= '0';
elsif (( a_in='0' and b_in='0' and c_in = '1')
or (a_in='0' and b_in='1' and c_in = '0')
or (a_in='1' and b_in='0' and c_in = '0')) then
sum <= '1';carry <= '0';
elsif (( a_in='0' and b_in='1' and c_in = '1')
or (a_in='1' and b_in='0' and c_in = '1')
or (a_in='1' and b_in='1' and c_in = '0')) then
sum <= '0';carry <= '1';
elsif(a_in='1' and b_in='1' and c_in = '1') then
sum <= '1';carry <= '1';
end if;
end process;
end Behavioral;

Verilog File Name:

FullAdder_Behav.v
//FullAdder - Behavioral Model
module FullAdder_Behav( a_in, b_in, c_in, sum, carry );
input a_in, b_in, c_in;
output sum, carry;
wire a_in, b_in, c_in;
reg sum, carry;
always @ ( a_in, b_in, c_in)
begin
if(a_in==0 & b_in==0 & c_in==0)
begin
sum = 0;
carry = 0;
end
else if (( a_in==0 & b_in==0 & c_in == 1)
| (a_in==0 & b_in==1 & c_in == 0)
| (a_in==1 & b_in==0 & c_in == 0))
begin
sum  = 1;
carry = 0;
end
else if (( a_in==0 & b_in==1 & c_in == 1)
| (a_in==1 & b_in==0 & c_in == 1)
| (a_in==1 & b_in==1 & c_in == 0))
begin
sum  = 0;
carry = 1;
end
else if(a_in==1 & b_in==1 & c_in == 1)
begin
sum = 1;
carry = 1;
end
end
endmodule