HDL Programming for Binary Any Sequence up down 4bit Counter

VHDL File Name:
bin_counter_any_seq_4bit.vhd
-- Binary Any Sequence up down 4bit counter
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity bin_counter_any_seq is
Port ( clk,rst,load,updown : in  STD_LOGIC;
d_in :in  STD_LOGIC_VECTOR( 3 downto 0);
bin_out : out  STD_LOGIC_VECTOR (3 downto 0));
end bin_counter_any_seq;
architecture Behavioral of bin_counter_any_seq is
signal temp: std_logic_vector(3 downto 0):= "0000";
begin
process(clk, rst)
begin
if(rst = '1') then
temp <= "0000";
elsif(load = '1') then
temp <= d_in;
elsif ( clk'event and clk='1' and load = '0') then
if ( updown = '1') then
temp <= temp+'1';
else
temp <= temp-'1';
end if;
end if;
end process;
bin_out <= temp ;
end Behavioral;

Verilog File Name:
bin_counter_any_seq_4bit.v
// Binary Any Sequence Up Down Counter
module any_seq_bin ( rst,load, clk,din,updown, count);
input rst,clk,updown,load;
input [3:0] din;
output [3:0] count;
reg [3:0] count;
always @(posedge clk)
if(rst)
count = 4'b0000;
else
if(load)
count = din;
else
if (updown)
count = count + 4'b0001;
else
count = count - 4'b0001;
endmodule