HDL Programming for BCD Asynchronous Reset 4bit Counter

VHDL File Name:
bcd_counter_async_4bit.vhd
-- BCD asynchronous reset 4bit counter
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity bcd_counter_async is
Port ( clk,rst : in  STD_LOGIC;
bcd_out : out  STD_LOGIC_VECTOR (3 downto 0));
end bcd_counter_async;
architecture Behavioral of bcd_counter_async is
signal temp: std_logic_vector(3 downto 0):= "0000";
begin
process(clk,rst)
begin
if(rst = '1' or temp = "1010") then
temp <= "0000";
elsif ( clk'event and clk='1') then
temp <= temp+'1';
end if;
end process;
bcd_out <= temp ;
end Behavioral;

Verilog File Name:
bcd_counter_async_4bit.v
// BCD asynchronous reset 4bit counter
module bcd_async ( rst, clk, count);
input rst,clk;
output [3:0] count;
reg [3:0] count;
initial
begin
count = 4'd0;
end
always @(posedge clk or posedge rst)
if(rst)
count = 4'd0;
else
if(count < 4'd9 )
count = count + 4'd1;
else
count = 4'd0;
endmodule