HDL Programming for BCD Synchronous Reset 4bit Counter

VHDL File Name:
bcd_counter_sync_4bit.vhd
--BCD Synchronous  reset 4bit counter
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity bcd_counter_sync is
Port ( clk,rst : in  STD_LOGIC;
bcd_out : out  STD_LOGIC_VECTOR (3 downto 0));
end bcd_counter_sync;
architecture Behavioral of bcd_counter_sync is
signal temp: std_logic_vector(3 downto 0);
begin
process(clk)
begin
if ( clk'event and clk='1') then
if(rst = '1' or temp = "1001") then
temp <= "0000";
else
temp <= temp+'1';
end if;
end if;
end process;
bcd_out <= temp ;
end Behavioral;

Verilog File Name:
bcd_counter_sync_4bit.v
// BCD synchronous reset 4bit counter
module bcd_sync ( rst, clk, count);
input rst,clk;
output [3:0] count;
reg [3:0] count;
initial
begin
count = 4'd0;
end
always @(posedge clk)
if(rst)
count = 4'd0;
else
if(count < 4'd9 )
count = count + 4'd1;
else
count = 4'd0;
endmodule