HDL programming for Binary Asynchronous Reset 4bit Counter

VHDL File Name:
bin_counter_async_4bit.vhd
--Binary Asynchronous reset 4bit counter
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity bin_counter_async_4bit is
Port ( clk,rst : in  STD_LOGIC;
bin_out : out  STD_LOGIC_VECTOR (3 downto 0));
end bin_counter_async_4bit;
architecture Behavioral of bin_counter_async_4bit is
signal temp: std_logic_vector(3 downto 0);
begin
process(clk,rst)
begin
if(rst = '1') then
temp <= "0000";
elsif ( clk'event and clk='1') then
temp <= temp+'1';
end if;
end process;
bin_out <= temp ;
end Behavioral;

Verilog File Name:
bin_counter_async_4bit.v
// Binary asynchronous reset 4bit counter
module bin_async_4bit ( rst, clk, count);
input rst,clk;
output [3:0] count;
reg [3:0] count;
initial
begin
count = 4'b0000;
end
always @(posedge clk or posedge rst)
if(rst)
count = 4'b0000;
else
count = count + 4'b0001;
endmodule