HDL Programming for D flip-flop

VHDL File Name:

d_ff.vhd
-- D Flip Flop
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity d_ff is
Port ( d,clk,rst : in  STD_LOGIC;
q,qb : out  STD_LOGIC);
end d_ff;
architecture Behavioral of d_ff is
signal temp : std_logic := '0';
begin
process(clk,rst)
begin
if(rst = '1')  then
temp <= '0';
elsif(clk'event and clk = '1') then
temp <= d;
end if;
end process;
q <= temp;
qb <= not temp;
end Behavioral;

Verilog File Name:

d_ff.v
//Async D Flip Flop
module d_ff( d  , clk    , reset , q ,qb );
input d, clk, reset ;
output q,qb;
reg q,qb;
always @ ( posedge clk or posedge reset)
if (reset)
begin
q = 1'b0;
qb=~q;
end
else
begin
q = d;
qb=~q;
end
endmodule