HDL Programming for JK flip-flop(Both VHDL & Verilog)

VHDL File Name:

jk_ff.vhd
--JK Flip Flop
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity jk_ff is
Port ( j,k,rst,clk : in  STD_LOGIC;
q,qb : out  STD_LOGIC);
end jk_ff;
architecture Behavioral of jk_ff is
signal temp : std_logic := '0';
begin
process(clk,rst)
begin
if(rst = '1') then
temp <= '0';
elsif(clk'event and clk = '1') then
if(j = '0' and k ='0') then
temp <= temp;
elsif(j = '0' and k ='1') then
temp <= '0';
elsif(j = '1' and k ='0') then
temp <= '1';
elsif(j = '1' and k ='1') then
temp <= not temp;
end if;
end if;
end process;
q <= temp;
qb <= not temp;
end Behavioral;

Verilog File Name:

jk_ff.v
//Async JK Flip Flop
module jk_ff( jk  , clk    , reset , q ,qb );
input [1:0] jk;
input clk, reset ;
output q,qb;
reg q,qb;
always @ ( posedge clk or posedge reset)
if (reset)
begin
q = 1'b0;
qb = ~q;
end
else
begin
case (jk)
2'd0 : q = q;
2'd1 : q = 1'b0;
2'd2 : q = 1'b1;
2'd3 : q = ~q;
endcase
qb = ~q;
end
endmodule